A typical computer memory is designed to store many thousands of bits of information. These bits are stored in individual memory cells that are generally organized in rows and columns to make efficient use of space on a semiconductor substrate containing the memory. A commonly used cell architecture is the six transistor static random access memory (6T SRAM) cell. As computer memory has increased in the number of bits needed, effort has been placed on reducing the size of an individual memory cell. In particular, dynamic random access memory (DRAM) cells having fewer than six transistors are of increasing interest. However, each DRAM cell requires periodic refreshing of its memory state. Although this refresh rate has been adequate in the past, further improvements in the refresh interval would be beneficial in the art.